Z80 Emulacja

Instrukcje

LD r, R Operacja r←R M-1; T-4; 4MHz E.T. 1,00

01rrrRRR

A 111
B 000
C 001
D 010
E 011
H 100
L 101

Jeżeli rrr lub RRR = 110 to (HL)

LD r, n Operacja r←n M-2; T-7 (4, 3); 4MHz E.T. 1,75

00rrr110
nnnnnnnn

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD r, (HL) Operacja r←(HL) M-2; T-7 (4, 3); 4MHz E.T. 1,75

01rrr110

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD r, (IX+d) Operacja r←(IX+d) M5; T-19 (4, 4, 3, 5, 3); 4MHz E.T. 2,50

11011101 0xDD
01rrr110
dddddddd

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD r, (IY+d) Operacja r←(IY+d) M5; T-19 (4, 4, 3, 5, 3); 4MHz E.T. 4,75

11111101 0xFD
01rrr110
dddddddd

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD (HL), r Operacja (HL)←r M-2; T-7 (4, 3); 4MHz E.T. 1,75

01110rrr

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD (IX+d), r Operacja (IX+d)←r M-5; T-19 (4, 4, 3, 5, 3); 4MHz E.T. 4,75

11011101 0xDD
01110rrr
dddddddd

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD (IY+d), r Operacja (IY+d)←r M-5; T-19 (4, 4, 3, 5, 3); 4MHz E.T. 4,75

11111101 0xFD
01110rrr
dddddddd

A 111
B 000
C 001
D 010
E 011
H 100
L 101

LD (HL), n Operacja (HL)←n M-3; T-10 (4, 3, 3); 4MHz E.T. 2,50

00110110 0x36
nnnnnnnn

LD (IX+d), n Operacja (IX+d)←n M-3; T-10 (4, 3, 3); 4MHz E.T. 2,50

11011101 0xDD
00110110 0x36
dddddddd
nnnnnnnn

LD (IY+d), n Operacja (IY+d)←n M-5; T-19 (4, 4, 3, 5, 3); 4MHz E.T. 2,50

11111101 0xFD
00110110 0x36
dddddddd
nnnnnnnn

LD A, (BC) Operacja A←(BC) M-2; T-7 (4, 3); 4MHz E.T. 1,75

00001010 0x0A

LD A, (DE) Operacja A←(DE) M-2; T-7 (4, 3); 4MHz E.T. 1,75

00011010 0x1A

LD A, (nn) Operacja A←(nn) M-4; T-13 (4, 3, 3, 3); 4MHz E.T. 3,25

00111010 0x3A
nnnnnnnn
nnnnnnnn

LD (BC), A Operacja (BC)←A M-2; T-7 (4, 3); 4MHz E.T. 1,75

00000010 0x02

LD (DE), A Operacja (DE)←A M-2; T-7 (4, 3,); 4MHz E.T. 1,75

00010010 0x12

LD (nn), A Operacja (nn)←A M-4; T-13 (4, 3, 3, 3); 4MHz E.T. 3,25

00110010 0x32
nnnnnnnn
nnnnnnnn

LD A, I Operacja A←I M-2; T-9 (4, 5); 4MHz E.T. 2,25

11101101 0xED
01011110 0x57

Condition Bits Affected S is set if the I Register is negative; otherwise, it is reset. Z is set if the I Register is 0; otherwise, it is reset. H is reset. P/V contains contents of IFF2. N is reset. C is not affected. If an interrupt occurs during execution of this instruction, the Parity flag contains a 0.

LD A, R Operacja A←R M-2; T-9 (4, 5); 4MHz E.T. 2,25

11101101 0xED
01011111 0x5F

Condition Bits Affected S is set if, R-Register is negative; otherwise, it is reset. Z is set if the R Register is 0; otherwise, it is reset. H is reset. P/V contains contents of IFF2. N is reset. C is not affected. If an interrupt occurs during execution of this instruction, the parity flag contains a 0.

LD I, A Operacja I←A M-2; T-9 (4, 5); 4MHz E.T. 2,25

11101101 0xED
01001110 0x47

LD R, A Operacja R←A M-2; T-9 (4, 5); 4MHz E.T. 2,25

11101101 0xED
01001111 0x4F